Reference is now made to FIG. 1 which illustrates a circuit diagram of a conventional non-volatile memory cell 10. The cell 10 comprises a first transistor 12 and a second transistor 14. The first transistor 12 is a memory transistor and is configured with a floating gate structure 16 known to those skilled in the art. The floating gate structure 16 can be implemented in a number of ways: for example through the use specific process steps or by the use of a capacitor connected at the gate of a conventional NMOS transistor. The wordline (WL) for the cell 10 is connected to the gate (control terminal) of the memory floating gate first transistor 12. The second transistor 14, comprising for example a conventional NMOS transistor, functions as a select transistor for the memory floating gate first transistor 12. A select signal (SEL) is applied to the gate of transistor 14. The source-drain paths of the first and second transistors 12 and 14 are connected in series. The drain terminal of the floating gate first transistor 12 is coupled to a bit-line (BL) and a source terminal of the select second transistor 14 is coupled to a source-line (SL). The transistors 12 and 14 are formed in a common P-well (PW). To program the cell 10, charge is stored at floating gate structure 16. The construction, configuration and operation of the cell 10 are well known to those skilled in the art.
FIG. 2 illustrates a block diagram of an exemplary non-volatile memory 20 including a plurality of cells 10 arranged in an array 22. The memory 20 may be implemented as a discrete memory circuit or embedded with other circuitry, such as processing circuitry, in a system on chip (SoC) integrated circuit. FIG. 3 illustrates the details of a portion of the array 22 within memory 20, and in particular shows a subset of the array formed by cells 10 arranged in two sectors. The illustrated number of cells is exemplary only, and those skilled in the art understand that each sector may include many more cells and that the memory will include many more sectors. A word-line (WL) driver circuit 24 is used to select/de-select the word-lines in different operations by applying signals to the gates of the memory floating gate first transistors 12 of individual ones or groups of cells 10. A select line (SEL) driver circuit 26 is used to select/de-select memory cells 10 in different operations by applying signals to the gates of the select transistors 14 of individual ones or groups of cells 10. The voltage levels of the signals applied by the SEL-driver 26 and WL-driver 24 control the operation to select or de-select a particular memory cell 10 as well operate the cell in a number of different operating modes including programming and erase. A column decoder circuit 28 and pre-decoder circuit 30 are used to select the bit-lines (BL< >) and source-lines (SL< >) of the one or more memory cells 10 desired in the programming or erase operations. A charge-pump 32 generates the on-chip high voltage(s) required during program and erase operations for application to specific nodes of the memory cells. The voltage generator block 34 is included as a part of the charge pump 32 for the memory. The high voltages and other multiple voltages are generated by the block 34 from the pumped voltage and routed to different blocks of the memory for selection and application to the memory cells.
The programming operation of the cell 10 utilizes the well-known Fowler-Nordheim (FN) tunneling effect. To perform FN-tunneling, high voltages are required which are generated on-chip through the charge-pump 32 and voltage generator 34 for application to the cells 10. The FN process is well known in the art. Biasing of the nodes of the memory cell in a particular way achieves the FN tunneling effect and programs a desired data value at a selected memory cell. Reference is now made to Table 1 which illustrates the different voltages required in an exemplary implementation to bias a memory cell 10 during a programming operation:
BLBL(programmed(not program-WLSEL0/SEL1cell)med cell)PWSLSelectedVHIGH0/00(VHIGH/3)00 orsector(VHIGH/3)Non-00/00(VHIGH/3)00 orselected(VHIGH/3)sector
Reference is now made to FIG. 4A which illustrates, in the context of a subset of the array and column decoding circuitry, the programming operation conditions and a resulting leakage path situation. The required voltages are provided with response to a selected sector and non-selected sector (see, FIG. 3). With respect to the selected sector, in order to program a memory cell 10, a VHIGH voltage is applied through the word-line to the gate of the memory floating gate first transistor 12 for the cell 10 being programmed and the bit-lines of that cell are driven to logic “0”. The voltage VHIGH is well in excess of logic “1” voltage, for example comprising a voltage of about 15-18V. Also within the selected sector, and with respect to each memory cell 10 that is not being programmed, the VHIGH voltage is applied through the word-line to the gate of the memory floating gate first transistor 12 and the bit-lines of that memory cell 10 are driven to a VHIGH/3 voltage (provided by the voltage generator 34) in order to inhibit the programming operation. During the programming operation, the select transistors 14 in all cells 10 are turned OFF by driving the gate terminals of the select transistors to logic “0” (i.e., applying a Vgs=0).
The array configuration shown in FIG. 3 provides for all bit-lines in the array to be shared across sectors. Thus, the voltages applied to the bit-lines with respect to selected cells 10 in one sector (the selected sector) are also applied to the cells in other sectors (the non-selected sectors).
It is evident that in applying the VHIGH/3 voltage at some of the bit-lines in order to inhibit the programming of non-selected cells in the selected sector, this will force some of the bit-lines at high voltage. Within the selected sector, the select transistor 14 accordingly sees a Vds at the VHIGH/3 voltage because the memory cell 10 is fully ON. However, the select transistor has an assumed state of being perfectly switched OFF because the Vgs=0 for this transistor. Nonetheless, this select transistor 14 exhibits leakage (reference 40 in FIG. 4A) of the sub-threshold conduction type due to the presence of a high Vds at the NMOS select transistor 14. The sub-threshold conduction for the NMOS select transistor is high, and the problem with this leakage is exacerbated at fast corners and high temperature. With respect to the non-selected memory cells in the non-selected sectors, and assuming the non-selected cells are depleted, a high Vds is also seen across the associated NMOS select transistors and this results in a further contribution of sub-threshold array leakage. Indeed, the overall leakage in programming operation can be very high with memories having a larger density cut. For example, for a cut-size of 4 Kbit, this leakage is ˜600 uA @ 150 degrees C.
FIG. 4B illustrates simulation results for a memory of the type shown in FIG. 4A and having a 4 Kbit array density operating in programming mode. The simulation results show that during a worst case the array leakage exceeds 600 uA. This leakage will become the current load for the charge-pump during programming.
A similar concern with leakage exists with respect to the erase operation which is also a high voltage operation. The erasing operation of the cell 10 also utilizes the well-known Fowler-Nordheim (FN) tunneling effect. To perform FN-tunneling, high voltages are required which are generated on-chip through the charge-pump 32 for application to the cells 10. The FN process is well known in the art. Biasing of the nodes of the memory cell in a particular way achieves the FN tunneling effect and erases a desired data value at a selected memory cell. Reference is now made to Table 2 which illustrates the different voltages required to bias a memory cell 10 during an erase operation:
BLBL(programmed(not program-WLSEL0/SEL1cell)med cell)PDPWSLSelected0VHIGHFloatingFloating0VHIGHVHIGHsectorNon-VHIGHVHIGHFloatingFloating0VHIGHVHIGHselectedsector
Reference is now made to FIG. 5A which illustrates, in the context of a subset of the array and column decoding circuitry, the erase operation conditions and the leakage path situation. In the erase operation, the word-line in the selected sector is driven to logic “0” and the p-well (PW) is biased at the VHIGH voltage generated by the charge-pump. Those skilled in the art recognize that parasitic diodes exist in the transistors 12 and 14 between the bulk-source junction and bulk-drain junction. So, the source and drain terminals of the memory cell will be charged to a voltage equal to VHIGH-Vt (where Vt is the threshold voltage of the bulk to source-drain junction). Because the bit-lines and source-lines of the whole array are shared, this high voltage of VHIGH-Vt is transferred to the drain terminal of the column decoding transistors within the column decoder 28. In order to protect a first level 44 of the column decoding transistors, the gate and source of the included first level transistors are biased during erase at a 2VHIGH/3 voltage level generated by the charge pump of the voltage generator block 34. Similarly, a next level 46 of column decoding sees a stress at the 2VHIGH/3 voltage. In order to protect the second level 46 of decoding, the gate and source of the included second level transistors are biased at the VHIGH/3 voltage level. The source terminals of the transistors in the second level 46 of the column decoding are also biased through pull-up transistors 48 in a program related circuitry 50 section (FIGS. 2 and 5A) to the VHIGH/3 voltage level (where the included pull-down transistors 54 are controlled in an OFF state by driving their gate terminals to logic “0”). The pull-down transistors 54, however, will see a Vds of the VHIGH/3 voltage level. There is accordingly a sub-threshold leakage current 56. Because the pull-up and pull-down transistor circuits 48/54 within the program related circuitry 50 are repeated in dependence on the number of source-lines and bit-lines and eventually the sector size, it will be understood that the larger the sector the greater the number of circuits 48/54 that are needed, and correspondingly the higher the sub-threshold leakage. For a sector size of 256 bits this leakage is around ˜100 uA @ 150 degrees C.
FIG. 5B illustrates simulation results for a memory of the type shown in FIG. 5A and having a 4 Kbit array density operating in erase mode. The simulation results show that during a worst case the array leakage exceeds 90 uA. This leakage will become the current load for the charge-pump during programming.
The leakages during programming and erase operations are not negligible and need to be supported by the on-chip charge-pump. The voltages VHIGH, 2VHIGH/3 and (VHIGH/3) are generated by voltage generator block 34 and specifically responsive to the operation of the charge-pump 32. It is thus noted that the leakage currents during both programming and erase become the current load for the charge-pump. If the charge-pump 32 is not able to support the array leakage, then the memory write and erase operations may fail or may be performed erroneously.
One solution to this problem is to design the charge pump 32 as a very low impedance circuit that can support the anticipated leakage during program and erase operations. A drawback of this solution is that the charge pump will occupy a larger amount of integrated circuit area (due for example to an increased size storage capacitor and additional pumping stages) and there will be a corresponding increase in power consumption. Additionally, this solution drives towards a chip that lacks modularity because any changes in the density of memory array will require a re-design of the charge-pump in order to support the leakage. Such a redesign may adversely affect circuit area and power consumption.
Further, while this leakage is very large in fast corner and higher temperature conditions, in typical operating conditions it is noted that no or very little leakage may occur. The provision of a strong charge-pump to support this anticipated leakage at the fast corner and high temperature conditions accordingly presents an over-design for the typical operating conditions where current load for the charge-pump is lower. In this case, with a stronger charge pump, the charge pump ripple will be more prominent. It may not be possible to control the ripple and the reliability of the memory operation could then suffer.
There is accordingly a need in the art to reduce or remove the leakage in a non-volatile memory array during program and erase operations which will help in reducing the area occupied by the charge pump and further reduce the power consumed not only by the charge pump but also with respect to the entire system (for example, the system on chip (SoC) which includes the memory array).